maximize
[1] S. Klupsch, M. Ernst, S. A. Huss, M. Rumpf, and R. Strzodka. Real time image processing based on reconfigurablhimoe hardware acceleration. In Heterogeneous reconfigurable Systems on Chip, 2002.
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This paper is concerned with a substantial speed up of image processing methods on 2D and 3D images making use of modern FPGA (Field Programmable Gate Array) technology. The applications of this class of methods ranges from 2D and 3D image denoising and restoration, segmentation, morphological shape recovery and matching to vector field visualization and simulation. The described demonstrator is based on level set methods, but the proposed workflow allows to exchange the underlying mathematical methods easily. The FPGA based hardware implementation profits especially from the high parallelism in the algorithm and the moderate number precision required to preserve the qualitative effects of the mathematical models. Furthermore, different variants can be supported on the same hardware by uploading a new programming onto the FPGA. This will enable the use of these flexible image processing methods in applications where real time performance is indispensable.